1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) structures and more particularly to a sensing method for DRAM structures using a single-bitline voltage swing and variable bitline precharge voltage.
2. Description of the Background Art
U.S. Pat. No. 4,669,065 issued May 26, 1987 to Ohsawa and entitled, "DYNAMIC MEMORY APPARATUS HAVING A SENSE AMPLIFIER AND A REFERENCE VOLTAGE CONNECTION CIRCUIT THEREFOR" discloses a memory apparatus that has a dummy cell comprising two sets of series connections of MOS transistors and capacitors, respectively, connected to a pair of bitlines, which are connected to a sense amplifier of a flip-flop type, and a third MOS transistor having a source and a drain thereof connected between junction points of the MOS transistors and the capacitors of the dummy cell. The capacitors are charged at a high level potential and a low level potential, respectively, of the bitlines and then they are shorted to each other through the third MOS transistor so that they have a common potential of a middle potential level. The potential of the middle level can be supplied to a pair of input terminals to the flip-flop type sense amplifier as a reference potential signal. Thus, it is possible to assure a stable sensing operation by the sense amplifier which is free from an influence of a change in the potential of a substrate of the memory apparatus.
U.S. Pat. No. 4,792,928 issued Dec. 20, 1988 to Tobita entitled, "SEMICONDUCTOR MEMORY CIRCUIT WITH CONTROL OF BITLINE VOLTAGE BALANCING" describes a semiconductor memory circuit that includes a plurality of memory cell columns each comprising a plurality of memory cells connected to a bitline, at least a dummy cell connected to a bitline constituting a bitline pair with said bitline, a sense amplifier connected between said two bitlines, and at least a FET for balancing the voltages of said two bitlines; and a balance control circuit for detecting the termination of selection of a dummy word line which is provided for the control of the dummy cell and thereafter operating the FET.
U.S. Pat. No. 4,816,706 issued Mar. 28, 1989 to Dhong et al entitled, "SENSE AMPLIFIER WITH IMPROVED BITLINE PRECHARGING FOR DYNAMIC RANDOM ACCESS MEMORY" discloses a sense amplifier and decoupling device structure for integrated circuit memories wherein an embodiment of a cross-coupled sense amplifier includes two PMOS devices, the gates of which devices are grounded and clamp the downward voltage swing of the memory bitlines to the absolute value of the threshold voltage (VTP) of the grounded-gate PMOS devices in the sense amplifier. This limited voltage swing does not affect charge storage of storage capacitors because the absolute value of the threshold voltage (VT) of the cell transfer gate device is larger. Precharging the bitlines is achieved by equalizing the two bitlines, each initially charged to VDD and .vertline.VTP.vertline., respectively. One node of the sense amplifier retains a full VDD swing and is conveniently connected to the DATA bus. The sense amplifier bitline swing is limited to a swing of VDD-.vertline.VTP.vertline. and saves power without adversely affecting charge storage and the precharging level.
U.S. Pat. No. 4,669,065 issued May 26, 1987 to Ohsawa and entitled, "DYNAMIC MEMORY APPARATUS HAVING A SENSE AMPLIFIER AND A REFERENCE VOLTAGE CONNECTION CIRCUIT THEREFOR" discloses a method of making a dummy cell of a CMOS DRAM.
U.S. Pat. No. 4,816,706 issued Mar. 28, 1989 to Dhong et al entitled, "SENSE AMPLIFIER WITH IMPROVED BITLINE PRECHARGING FOR DYNAMIC RANDOM ACCESS MEMORY" discloses 2/3 VDD sensing with the limited bitline swing.
U.S. Pat. No. 4,792,928 issued Dec. 20, 1988 to Tobita and entitled, "SEMICONDUCTOR MEMORY CIRCUIT WITH CONTROL OF BIT LINE VOLTAGE BALANCING" discloses a method for precharging the bitlines at the end of a RAS cycle. The reference wordline with the dummy cells is monitored for initiating the precharging of the bitlines.
U.S. Pat. No. 5,036,492 issued Jul. 30, 1991 to Runaldue and entitled, "CMOS PRECHARGE AND EQUALIZATION CIRCUIT" discloses a precharging circuit for SRAM where the equalization and precharging of the bitlines are done without current bleeding devices.
U.S. Pat. No. 4,998,222 issued Mar. 5, 1991 to Sussman and entitled, "DYNAMIC RANDOM ACCESS MEMORY WITH INTERNALLY GATED RAS" discloses a bitline precharging circuit which is controlled by an internally RAS gated clock.
U.S. Pat. No. 4,943,960 issued Jul. 24, 1990 to Komatsu et al and entitled, "SELF-REFRESHING OF DYNAMIC RANDOM ACCESS MEMORY DEVICE AND OPERATING METHOD THEREFOR" discloses a detection circuit which detects the self-refresh mode and a voltage generator which precharges the bitlines.
U.S. Pat. No. 4,943,952 issued Jul. 24, 1990 to Terayama and entitled, "SEMICONDUCTOR MEMORY CIRCUIT WITH IMPROVED BIT LANE PRECHARGE CIRCUIT" discloses a bitline precharge circuit which is based on the concept of capacitive charge sharing.
U.S. Pat. No. 4,926,381 issued May 15, 1990 to Fujii entitled, "SEMICONDUCTOR MEMORY CIRCUIT WITH SENSING ARRANGEMENT FREE FROM MALFUNCTION" discloses a sensing method where the sense amplifier is totally isolated from the bitline by an isolator during sensing.
U.S. Pat. No. 4,916,667 issued Apr. 10, 1990 to Miyabayashi et al entitled, "DYNAMIC RANDOM ACCESS MEMORY HAVING FOLDED BIT LINE-SHARED SENSE AMPLIFIERS" discloses a sensing method where the sense amplifiers are shared by the two memory array.
U.S. Pat. No. 4,852,064 issued Jul. 25, 1989 to Kim et al and entitled, "PRECHARGE CIRCUIT FOR USE IN A SEMICONDUCTOR MEMORY DEVICE" discloses a precharging circuit for SRAM where the precharging is done in two stages.
U.S. Pat. No. 4,833,654 issued May 23, 1989 to Suwa et al entitled, "METHOD OF AND CIRCUITRY FOR GENERATING STAGGERED RESTORE TIMING SIGNALS IN BLOCK PARTITIONED DRAM" discloses a method for generating staggered restore timing signals in block partitioned DRAM.
U.S. Pat. No. 4,794,571 issued Dec. 27, 1988 to Uchida and entitled, "DYNAMIC READ-WRITE RANDOM ACCESS MEMORY" discloses a DRAM with reduced leakage by biasing the bitlines to a voltage between that of the wordlines and the voltage of the drain of the MOS transistor.